S1D13A05B00B200 Datasheet, PDF (139/184 Pages) EPCOS – LCD/USB Companion Chip

Epson Research and Development
Vancouver Design Center
Page 139
Endpoint 1 Index Register
REG[4010h]
Default = 00h
15
14
13
n/a
7
6
5
n/a
12
11
4
3
Read/Write
10
9
8
Endpoint 1 Index bits 2-0 (RO)
2
1
0
bits 2-0
Endpoint 1 Index Register Bits [2:0].
This register determines which Endpoint 1 Receive Mailbox is accessed when the End-
point 1 Receive Mailbox Data register is read. This register is automatically incremented
after the Endpoint 1 Receive Mailbox Data register is read. This index register wraps
around to zero when it reaches the maximum count (7).
Endpoint 1 Receive Mailbox Data Register
REG[4012h]
Default = 00h
n/a
15
14
13
12
11
10
Endpoint 1 Receive Mailbox Data bits 7-0
7
6
5
4
3
2
Read Only
9
8
1
0
bits 7-0
Endpoint 1 Receive Mailbox Data Bits [7:0].
This register is used to read data from one of the receive mailbox registers. Data is
returned from the register selected by the Endpoint 1 Index Register. The eight receive
mailbox registers are written by a USB bulk transfer to endpoint 1, and can be used to pass
messages from the USB host to the local CPU. The format and content of the messages are
user defined. If enabled, USB writes to this register can generate an interrupt.
Endpoint 2 Index Register
REG[4018h]
Default = 00h
15
14
13
n/a
7
6
5
n/a
12
11
4
3
Read/Write
10
9
8
Endpoint 2 Index bits 2-0
2
1
0
bits 2-0
Endpoint 2 Index Register Bits [2:0].
This register determines which Endpoint 2 Transmit Mailbox is accessed when the End-
point 2 Transmit Mailbox Data register is read or written. This register is automatically
incremented after the Endpoint 2 Transmit Mailbox Data port is read or written. This
index register wraps around to zero when it reaches the maximum count (7).
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
S1D13A05
X40A-A-001-07