EN25S40A Datasheet, PDF (9/68 Pages) Eon Silicon Solution Inc. – 4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

EN25S40A
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
WSE bit. The Write Suspend Erase Status (WSE) bit indicates when an Erase operation has been
suspended. The WSE bit is “1” after the host issues a suspend command during an Erase operation.
Once the suspended Erase resumes, the WSE bit is reset to “0”.
WSP bit. The Write Suspend Program Status (WSP) bit indicates when a Program operation has been
suspended. The WSP is “1” after the host issues a suspend command during the Program operation.
Once the suspended Program resumes, the WSP bit is reset to “0”.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the EN25S40A
provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Half Block Erase (HBE) / Block Erase (BE) instruction completion or Chip Erase
(CE) instruction completion
z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Status Register Content
Memory Content
BP3 BP2
Bit Bit
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Areas
None
Block 7
Block 6 to 7
Block 4 to 7
Block 2 to 7
Block 1 to 7
All
All
None
Block 0
Block 0 to 1
Block 0 to 3
Block 0 to 5
Block 0 to 6
All
All
Addresses
None
070000h-07FFFFh
060000h-07FFFFh
040000h-07FFFFh
020000h-07FFFFh
010000h-07FFFFh
000000h-07FFFFh
000000h-07FFFFh
None
000000h-00FFFFh
000000h-01FFFFh
000000h-03FFFFh
000000h-05FFFFh
000000h-06FFFFh
000000h-07FFFFh
000000h-07FFFFh
Density(KB) Portion
None
64KB
128KB
256KB
384KB
448KB
512KB
512KB
None
64KB
128KB
256KB
384KB
448KB
512KB
512KB
None
Upper 1/8
Upper 2/8
Upper 4/8
Upper 6/8
Upper 7/8
All
All
None
Lower 1/8
Lower 2/8
Lower 4/8
Lower 6/8
Lower 7/8
All
All
This Data Sheet may be revised by subsequent versions
9
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2013/12/30
www.eonssi.com