EN25S40A Datasheet, PDF (21/68 Pages) Eon Silicon Solution Inc. – 4 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

EN25S40A
WSE bit. The Write Suspend Erase Status (WSE) bit indicates when an Erase operation has been
suspended. The WSE bit is “1” after the host issues a suspend command during an Erase operation.
Once the suspended Erase resumes, the WSE bit is reset to “0”.
WSP bit. The Write Suspend Program Status (WSP) bit indicates when a Program operation has been
suspended. The WSP is “1” after the host issues a suspend command during the Program operation.
Once the suspended Program resumes, the WSP bit is reset to “0”.
Fail bit. The fail bit, volatile bit, it will latched high when erase or program or WRSR failed. It will be
reset after new embedded program and erase cycle re-stared or power on or software reset.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Suspend or
Write Resume cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in
progress.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 12. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is t_W) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
The instruction sequence is shown in Figure 12.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
Figure 12. Write Status Register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc.,
Rev. A, Issue Date: 2013/12/30
www.eonssi.com