EN25Q64 Datasheet, PDF (23/60 Pages) Eon Silicon Solution Inc. – 64 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

Table 7. Suspend Status Register Bit Locations
EN25Q64
S7
S6
S5
S4
WIP
(Write In
Progress bit)
(Note 1)
1 = write
operation
0 = not in write
operation
volatile bit
Reserved
bit
Fail bit
index
1 = erase or
program or
WRSR
failed
0 = passed
volatile bit
Reserved
bit
S3
WSP
(Write Suspend
Program bits)
1 = Program
suspended
0 = Program is
not suspended
volatile bit
S2
S1
S0
WSE
WEL
(Write Suspend (Write Enable
Erase status bit)
Latch)
1 = Erase
suspended
0 = Erase is not
suspended
1 = write enable
0 = not write
enable
Reserved
bit
volatile bit
volatile bit
Note:
1. When executed the (RDSSR) (09h) command, the WIP (S7) value is the same as WIP (S0) in table 6.
2. Default at Power-up is “0”
The status and control bits of the Suspend Status Register are as follows:
Reserved bit. Suspend Status register bit locations 0, 4 and 6 are reserved for future use. Current
devices will read 0 for these bit locations. It is recommended to mask out the reserved bit when testing
the Suspend Status Register. Doing this will ensure compatibility with future devices.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Suspend or Write Resume instruction is accepted.
WSE bit. The Write Suspend Erase Status (WSE) bit indicates when an Erase operation has been
suspended. The WSE bit is “1” after the host issues a suspend command during an Erase operation.
Once the suspended Erase resumes, the WSE bit is reset to “0”.
WSP bit. The Write Suspend Program Status (WSP) bit indicates when a Program operation has been
suspended. The WSP is “1” after the host issues a suspend command during the Program operation.
Once the suspended Program resumes, the WSP bit is reset to “0”.
Fail bit. The fail bit, volatile bit, it will latched high when erase or program or WRSR failed. It will be
reset after new embedded program and erase cycle re-stared or power on or software reset.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Suspend or
Write Resume cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in
progress.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is t_W) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
This Data Sheet may be revised by subsequent versions
23
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2009/10/19
www.eonssi.com