EN25Q64 Datasheet, PDF (18/60 Pages) Eon Silicon Solution Inc. – 64 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25Q64
Enable Quad I/O (EQIO) (38h)
The Enable Quad I/O (EQIO) instruction will enable the flash device for Quad SPI bus operation. Upon
completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a
power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 6. The device did not
support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual Input/Output
FAST_READ (BBh) modes while the Enable Quad I/O (EQIO) (38h) turns on.
Figure 6. Enable Quad I/O Sequence Diagram
Reset Quad I/O (RSTQIO) (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. The device accepts either Standard SPI ( 8 clocks ) or Quad SPI ( 2 clocks) command
cycles. For Standard SPI, DQ [3:1] are don’t care for this command, but should be driven to V_IH or V_IL.
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase
(BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 8.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 7. Write Enable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
18
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2009/10/19
www.eonssi.com