EN29F002A Datasheet, PDF (22/35 Pages) Eon Silicon Solution Inc. – 2 Megabit (256K x 8-bit) Flash Memory

Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
EN29F002A / EN29F002AN
Parameter
Symbols
JEDEC Standard
t_AVAV
t_RC
Description
Read Cycle Time
Speed Options
Test Setup
-45 -55 -70 -90 Unit
Min 45 55 70 90 ns
t_AVQV t_ACC
t_ELQV
t_CE
t_GLQV t_OE
Address to Output Delay
CE = V_IL ^{Max 45 55 70}
90
ns
Chip Enable To Output Delay
OE ₌ V_IL
OE ₌ V_IL ^{Max 45 55 70}
90
ns
Output Enable to Output Delay
Max 25 30 30 35 ns
t_EHQZ t_DF
Chip Enable to Output High Z
Max 10 15 20 20 ns
t_GHQZ t_DF
Output Enable to Output High Z
Max 10 15 20 20 ns
t_AXQX t_OH
t_Ready
Output Hold Time from
Addresses, CE or OE ,
whichever occurs first
RESET Pin Low to Read
Mode (n/a for EN29F002AN)
Min
0
0
0
0
ns
Max _{20 20 20 20}
µs
Notes:
For -45,-55
For all others:
Vcc = 5.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
Vcc = 5.0V ± 10%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V
This Data Sheet may be revised by subsequent versions ₂₂ ©2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2003/03/26