EN29F010 Datasheet, PDF (14/35 Pages) Eon Silicon Solution Inc. – 1 Megabit (128K x 8-bit) 5V Flash Memory

EN29F010
DATA PROTECTION
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE = V_IL, W E = V_IL and OE = V_IH, the device will not accept commands on the rising edge of
WE.
Low V_CC Write Inhibit
During V_CC power-up or power-down_, the EN29F010 locks out write cycles to protect against any
unintentional writes. If V_CC < V_LOK, the command register is disabled and all internal program or
erase circuits are disabled. Under this condition, the device will reset to the READ mode.
Subsequent writes will be ignored until V_CC > V_LKO.
Write “Noise” Pulse Protection
Noise pulses less than 5ns on OE , CE or WE will neither initiate a write cycle nor change the
command register.
Logical Inhibit
If CE =V_IH or WE=V_IH, writing is inhibited. To initiate a write cycle, CE and W E must be a logical
“zero”. If CE , W E , and OE are all logical zero (not recommended usage), it will be considered a
write.
Sector Protect and Unprotect
The hardware sector protection feature disables both program and erase operations in any sector.
The hardware sector unprotection feature re-enables both program and erase operation in
previously protected sectors.
Sector protection/unprotection must be implemented using programming equipment. The procedure
requires a high voltage (V_ID) on address pin A9 and the control pins. Contact Eon Silicon Solution,
Inc. for an additional supplement on this feature.
This Data Sheet may be revised by subsequent versions ₁₄ ©2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2003/10/20