EN25B64 Datasheet, PDF (14/37 Pages) Eon Silicon Solution Inc. – 64 Megabit Serial Flash Memory with Boot and Parameter Sectors

Figure 4. Hold Condition Waveform
EN25B64
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first.
Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#)
is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant
bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence
has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device
ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip
Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected,
and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses
after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at any
time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power
Down (RES ) minimum number of bytes specified has to be given, without which, the
command will be ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least
1 data byte), it will be ignored too. In the case of SE, exact 24-bit address is a must, any less
or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle
continues unaffected.
This Data Sheet may be revised by subsequent versions ₁₄ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2008/06/23