EN25B64 Datasheet, PDF (13/37 Pages) Eon Silicon Solution Inc. – 64 Megabit Serial Flash Memory with Boot and Parameter Sectors

Table 3a. Protected Area Sizes- Bottom Boot Sector Organization
EN25B64
Status Register
Content
BP2 BP1 BP0
Bit Bit Bit
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Memory Content
Protect Sectors
All
Sector 0 to 67
Sector 0 to 4
Sector 0 to 3
Sector 0 to 2
Sector 0 to 1
Sector 0
None
Addresses
000000h-7FFFFFh
000000h-3FFFFFh
000000h-00FFFFh
000000h-007FFFh
000000h-003FFFh
000000h-001FFFh
000000h-000FFFh
None
Density(KB)
Portion
8192KB
4096KB
64KB
32KB
16KB
8KB
4KB
None
All
Lower 1/2
Lower 1/128
Lower 1/256
Lower 1/512
Lower 1/1024
Lower 1/2048
None
Table 3b. Protected Area Sizes- Top Boot Sector Organization
Status Register
Content
BP2 BP1 BP0
Bit Bit Bit
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protect Sectors
None
Sector 131
Sector 130 to 131
Sector 129 to 131
Sector 128 to 131
Sector 127 to 131
Sector 64 to 131
All
Memory Content
Addresses
Density(KB)
None
7FF000h-7FFFFFh
7FE000h-7FFFFFh
7FC000h-7FFFFFh
7F8000h-7FFFFFh
7F0000h-7FFFFFh
400000h-7FFFFFh
000000h-7FFFFFh
None
4KB
8KB
16KB
32KB
64KB
4096KB
8192KB
Portion
None
Upper 1/2048
Upper 1/1024
Upper 1/512
Upper 1/256
Upper 1/128
Upper 1/2
All
Hold Function
The Hold (HOLD) signal is used to pause any serial communications with the device without reset-
ting the clocking sequence. However, taking this signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold
condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial
Clock (CLK) being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides
with Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts af-
ter Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock
(CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in
Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of
the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the
moment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is necessary to
drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from
going back to the Hold condition.
This Data Sheet may be revised by subsequent versions ₁₃ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2008/06/23