EN25B64 Datasheet, PDF (12/37 Pages) Eon Silicon Solution Inc. – 64 Megabit Serial Flash Memory with Boot and Parameter Sectors

EN25B64
All other instructions are ignored while the device is in the Deep Power-down mode. This can be
used as an extra software protection mechanism, when the device is not in active use, to protect the
device from inadvertent Write, Program or Erase instructions.
Status Register. The Status Register contains a number of status and control bits that can be read
or set (as appropriate) by specific instructions.
WIP bit. The WIP bit indicates whether the memory is busy with a Write Status Register, Program or
Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size
of the area to be software protected against Program and Erase instructions.
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit is operated in conjunction with the
Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal
allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the
Status Register (SRP, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as
normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR
command, the OTP sector is protected form program and erase operation. The OTP_LOCK bit can
only be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to
1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the
EN25B64 provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a
number of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction
completion or Bulk Erase (BE) instruction completion or
z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions
are ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions ₁₂ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2008/06/23