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EMLS232TA Datasheet, PDF (9/14 Pages) Emerging Memory & Logic Solutions Inc – 512K x 32 x 4Banks Low Power SDRAM Specificaton
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EMLS232TA Series
512K x 32 x 4Banks Low Power SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
tDAL(min)
Last data in to new col. address delay
tCDL(min)
Last data in to burst stop
tBDL(min)
Auto refresh cycle time
tARFC(min)
Exit self refresh to active command
tSRFX(min)
Col. address to col. address delay
tCCD(min)
Number of valid output data
CAS latency=3
Number of valid output data
CAS latency=2
Number of valid output data
CAS latency=1
Value
15
22.5
22.5
45
70,000
67.5
15
tRDL + tRP
1
1
80
120
1
2
1
-
Unit
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CLK
CLK
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CLK
Note
1
1
1
1
1
2
2
2
3
4
ea
5
NOTE :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the
next higher integer.
2. Minimum dealy is required to complete write.
3. Maximum burst refresh cycle: 8
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev 0.3
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