HB54R5128KN-A75B Datasheet, PDF (8/16 Pages) Elpida Memory – 512MB DDR SDRAM SO DIMM

HB54R5128KN-A75B/B75B/10B
Block Diagram
/S1
/S0
DQS0
RS
DQS
/S
DQS ^/S
DQS4
RS
DQS ^/S
DQS ^/S
DM0
RS
DM
D0
DM D8
RS
DM4
DM D4
DM D12
DQ0 to DQ7
DQS1
DM1
DQ8 to DQ15
8 RS
RS
RS
8 RS
E DQS2
DM2
DQ16 to DQ23
O_DQS3
DM3
L^{DQ24 to DQ31}
RS
RS
8 RS
RS
RS
8 RS
I/O0 to I/O7
DQS _/S
DM _D1
I/O0 to I/O7
DQS
/S
DM _D2
I/O0 to I/O7
DQS
/S
DM _D3
I/O0 to I/O7
I/O0 to I/O7
DQS _/S
DM _D9
I/O0 to I/O7
DQS ^/S
DM _D10
I/O0 to I/O7
DQS ^/S
DM _D11
I/O0 to I/O7
DQ32 to DQ39
DQS5
DM5
DQ40 to DQ47
8 RS
RS
RS
8 RS
DQS6
DM6
DQ48 to DQ55
DQS7
DM7
DQ56 to DQ63
RS
RS
8 RS
RS
RS
8 RS
I/O0 to I/O7
DQS _/S
DM D5
I/O0 to I/O7
DQS ^/S
DM _D6
I/O0 to I/O7
DQS /S
DM _D7
I/O0 to I/O7
I/O0 to I/O7
DQS _/S
DM D13
I/O0 to I/O7
DQS ^/S
DM _D14
I/O0 to I/O7
DQS /S
DM _D15
I/O0 to I/O7
Serial PD
BA0 to BA1
A0 to AN
/RAS
P ^/CAS
/WE
CKE0
CKE1
VCCSPD
r _VREF
VCC
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D7)
SDRAMs (D8 to D15)
SPD
SDRAMs (D0 to D15)
SDRAMs (D0 to D15), VCC and VCCQ
o _VSS
VCCID
Open
SDRAMs (D0 to D15), SPD
SDRAMs (D0 to D15), SPD
d * D0 to D15 : 256M bits DDR SDRAM
U0 : 2k bit EEPROM
uct ^{Rs : 22Ω}
SCL
SCL
SDA
SDA
SA0
A0 _U0
SA1
A1
SA2
A2 WP
CK0
/CK0
CK1
/CK1
CK2
/CK2
8 loads
8 loads
0 loads
Notes :
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VCCID strap connections:
(for memory device VCC, VCCQ)
Strap out (open): VCC = VCCQ
Strap in (closed): VCC ≠ VCCQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
Data Sheet E0189H40 (Ver. 4.0)
8