HB54R5128KN-A75B Datasheet, PDF (13/16 Pages) Elpida Memory – 512MB DDR SDRAM SO DIMM

HB54R5128KN-A75B/B75B/10B
Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
min.
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS,
/WE

90
pF
1
Input capacitance
CI2
CKE, /S CK, /CK

60
pF
1
Data and DQS input/output
capacitance
CO
DQ, DQS, DM

30
pF
1, 2
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
Timing Parameter Measured in Clock Cycle for Unbuffered DIMM
EParameter
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
O^{Write to read command delay (to input all data)}
Burst stop command to write command delay
(CL = 2)
(CL = 2.5)
Burst stop command to DQ High-Z
L ^{(CL = 2)}
(CL = 2.5)
Read command to write command delay (to output all data)
(CL = 2)
(CL = 2.5)
Pre-charge command to High-Z
P (CL = 2)
(CL = 2.5)
Write command to data in latency
Write recovery
r _{DM to data in latency}
Register set command to active or register set command
o _{Self refresh exit to non-read command}
Self refresh exit to read command
Power down entry
d Power down exit to command input
uct ^{CKE minimum pulse width}
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
tRWD
tRWD
tHZP
tHZP
tWCD
tWR
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
tCKEPW
Number of clock cycle
min.
max.
3 + BL/2
BL/2
2 + BL/2
2
3
2
2.5
2 + BL/2
3 + BL/2
2
2.5
1
2
0
2
10
200
1
1
1
Data Sheet E0189H40 (Ver. 4.0)
13