HB54R5128KN-A75B Datasheet, PDF (1/16 Pages) Elpida Memory – 512MB DDR SDRAM SO DIMM

DATA SHEET
512MB DDR SDRAM SO DIMM
HB54R5128KN-A75B/B75B/10B (64M words × 64 bits, 2 Banks) _Description
The HB54R5128KN is Double Data Rate (DDR)
SDRAM Module, mounted 256M bits DDR SDRAM
(HM5425801BTB) sealed in TCP package, and 1 piece
of serial EEPROM (2k bits EEPROM) for Presence
EDetect (PD). The HB54R5128KN is organized as 32M
× 64 × 2 banks mounted 16 pieces of 256M bits DDR
SDRAM. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
O^{speed data transfer is realized by the 2 bits prefetch-}
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. An outline of the products is 200-pin
L _{socket type package (dual lead out). Therefore, it}
makes high density mounting possible without surface
mount technology. It provides common data inputs
and outputs. Decoupling capacitors are mounted
beside each TCP on the module board.
P _{Note: Do not push the cover or drop the modules in}
order to protect from mechanical defects,
roduct ^{which would be electrical defects.}
Features
• 200-pin socket type package (dual lead out)
 Outline: 67.6mm (Length) × 31.75mm (Height) ×
3.80mm (Thickness)
 Lead pitch: 0.6mm
• 2.5V power supply (VCC)
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 133 MHz (max) (-A75B/B75B)
: 100 MHz (max) (-10B)
• Data inputs, outputs and DM are synchronized with
DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
 Burst read stop capability
• Programmable burst sequence
 Sequential
 Interleave
• Start addressing capability
 Even and Odd
• Programmable /CAS latency (CL): 2, 2.5
• 8192 refresh cycles: 7.8µs (8192row/64ms)
• 2 variations of refresh
 Auto refresh
 Self refresh
Document No. E0189H40 (Ver. 4.0) _{This product became EOL in May, 2004.}
Date Published September 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.