HB52D328DC-B Datasheet, PDF (7/24 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 100 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC100 SDRAM

HB52D328DC-B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
0 0 0 0 0 0 0 1 01
0
W latency
21
SDRAM module attributes
0 0 0 0 0 0 0 0 00
Non buffer
22
SDRAM device attributes:
0 0 0 0 1 1 1 0 0E
General
V_CC ± 10%
23
SDRAM cycle time
1 0 1 0 0 0 0 0 A0
(2nd highest CE latency)
(-A6B/A6BL) 10 ns
CL = 2
(-B6B/B6BL) 15 ns
1 1 1 1 0 0 0 0 F0
24
SDRAM access from Clock 0 1 1 0 0 0 0 0 60
(2nd highest CE latency)
(-A6B/A6BL) 6 ns
CL = 2
(-B6B/B6BL) 9 ns
1 0 0 1 0 0 0 0 90
25
SDRAM cycle time
0 0 0 0 0 0 0 0 00
(3rd highest CE latency)
Undefined
26
SDRAM access from Clock 0 0 0 0 0 0 0 0 00
(3rd highest CE latency)
Undefined
27
Minimum row precharge time 0 0 0 1 0 1 0 0 14
20 ns
28
Row active to row active min 0 0 0 1 0 1 0 0 14
20 ns
29
RE to CE delay min
0 0 0 1 0 1 0 0 14
20 ns
30
Minimum RE pulse width
0 0 1 1 0 0 1 0 32
50 ns
31
Density of each bank on
0 0 1 0 0 0 0 0 20
module
2 bank
128M byte
32
Address and command signal 0 0 1 0 0 0 0 0 20
2 ns
input setup time
33
Address and command signal 0 0 0 1 0 0 0 0 10
1 ns
input hold time
34
Data signal input setup time 0 0 1 0 0 0 0 0 20
2 ns
35
Data signal input hold time 0 0 0 1 0 0 0 0 10
1 ns
36 to 61 Superset information
0 0 0 0 0 0 0 0 00
Future use
62
SPD data revision code
0 0 0 1 0 0 1 0 12
Rev. 1.2B
63
Checksum for bytes 0 to 62 1 0 1 0 0 0 0 1 A1
161
(-A6B/A6BL)
(-B6B/B6BL)
0 0 1 0 0 0 0 1 21
33
64
Manufacturer’s JEDEC ID code 0 0 0 0 0 1 1 1 07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00
72
Manufacturing location
× × × × × × × × ××
*³ (ASCII-
8bit code)
Data Sheet E0084H10
7