HB52D328DC-B Datasheet, PDF (18/24 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 100 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC100 SDRAM

HB52D328DC-B
AC Characteristics (Ta = 0 to 65°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
Parameter
Symbol
System clock cycle time
(CE latency = 2)
t _CK
(CE latency = 3)
t _CK
CK high pulse width
t _CKH
CK low pulse width
t _CKL
Access time from CK
(CE latency = 2)
t _AC
(CE latency = 3)
t _AC
Data-out hold time
t _OH
CK to Data-out low impedance
t _LZ
CK to Data-out high impedance
t _HZ
Data-in setup time
t _DS
Data in hold time
t _DH
Address setup time
t _AS
Address hold time
t _AH
CKE setup time
t _CES
CKE setup time for power down exit t_CESP
CKE hold time
t _CEH
Command setup time
t _CS
Command hold time
t _CH
Ref/Active to Ref/Active command t_RC
period
Active to precharge command
t _RAS
period
Active command to column
t _RCD
command (same bank)
Precharge to active command
t _RP
period
Write recovery or data-in to
t _DPL
precharge lead time
Active (a) to Active (b) command t_RRD
period
Transition time (rise to fall)
t_T
Refresh period
t _REF
PC100
Symbol
Tclk
Tclk
Tch
Tcl
Tac
Tac
Toh
Tsi
Thi
Tsi
Thi
Tsi
Tpde
Thi
Tsi
Thi
Trc
Tras
Trcd
Trp
Tdpl
Trrd
HB52D328DC
-A6B/B6B/A6BL/B6BL
Min
Max
Unit
10
—
ns
10
—
ns
3
—
ns
3
—
ns
—
6
ns
—
6
ns
3
—
ns
2
—
ns
—
6
ns
2
—
ns
1
—
ns
2
—
ns
1
—
ns
2
—
ns
2
—
ns
1
—
ns
2
—
ns
1
—
ns
70
—
ns
50
120000 ns
20
—
ns
20
—
ns
20
—
ns
20
—
ns
1
5
ns
—
64
ms
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1, 5
1
1
1
1
1
1
1
1
1
1
Data Sheet E0084H10
18