HB52D328DC-B Datasheet, PDF (19/24 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 100 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC100 SDRAM

HB52D328DC-B
Notes: 1. AC measurement assumes t_T = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C_L = 50 pF.
3. t_LZ (max) defines the time at which the outputs achieves the low impedance state.
4. t_HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t_CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
input
2.4 V
2.0 V
0.4 V ^{0.8 V}
t_T
t_T
DQ
CL
Data Sheet E0084H10
19