HB52D328DC-B Datasheet, PDF(20/24 Page) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 100 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC100 SDRAM

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HB52D328DC-B Datasheet, PDF (20/24 Pages) Elpida Memory – 256 MB Unbuffered SDRAM S.O.DIMM 32-Mword × 64-bit, 100 MHz Memory Bus, 2-Bank Module (8 pcs of 16 M × 16 components) PC100 SDRAM

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HB52D328DC-B

Relationship Between Frequency and Minimum Latency

Parameter

Frequency (MHz)

tCK (ns)

Active command to column command (same

bank)

Active command to active command (same

bank)

Active command to precharge command

(same bank)

Precharge command to active command

(same bank)

Write recovery or data-in to precharge

command (same bank)

Active command to active command

(different bank)

Self refresh exit time

Last data in to active command

(Auto precharge, same bank)

Self refresh exit to command input

Precharge command to high impedance

(CE latency = 2)

(CE latency = 3)

Last data out to active command (auto

precharge) (same bank)

Last data out to precharge (early precharge)

(CE latency = 2)

(CE latency = 3)

Column command to column command

Write command to data in latency

DQMB to data in

DQMB to data out

CKE to CK disable

S to command disable

Power down exit to command input

HB52D328DC

-A6B/B6B/A6BL/B6BL

100

PC100

Symbol Symbol 10

Notes

I RCD

I RC

I RAS

= [IRAS + IRP]

I RP

I DPL

Tdpl 2

I RRD

I SREX

Tsrx

I APW

Tdal 4

= [IDPL + IRP]

I SEC

= [IRC]

I HZP

Troh 2

I HZP

Troh 3

I APR

I EP

I CCD

I WCD

I DID

I DOD

I CLE

I RSA

I CDD

I PEC

â1

â2

Tccd 1

Tdwd 0

Tdqm 0

Tdqz 2

Tcke 1

Tmrd 1

Data Sheet E0084H10

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