HM5425161B Datasheet, PDF (26/65 Pages) Elpida Memory – 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/ 16-Mword × 4-bit × 4-bank

;;;;;HM5425161B, HM5425801B, HM5425401B Series
Write operation: The burst length (BL) and the burst type (BT) of the mode register are referred when a
write command is issued. The burst length (BL) determines the length of a sequential data input by the write
command which can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The
starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B, AY0 to
AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (BA0/BA1) which
are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when the write command is issued. DQS,
DQSU/DQSL should be input as the strobe for the input-data and DM, DMU/DML as well during burst
operation. t_WPREH prior to the first rising edge of the DQS, the DQSU/DQSL should be set to Low and t_WPST
after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred
as write preamble. The last low period of DQS is referred as wrtie postamble.
Write Operation
t0
t1
t2
t3 t3.5 t4
t5
t6
t7
t8
CLK
CLK
Command _NOP
t_RCD
ACTV
NOP
WRITE
NOP
Address
DQS*
Din
Row
BL = 2
Column
t_WPREH
t_WPRES
in0 in1
t_WPST
BL = 4
in0 in1 in2 in3
BL = 8
DQS*:DQS,DQSU/DQSL
in0 in1 in2 in3 in4 in5 in6 in7
BL: Burst length
Data Sheet E0086H20
26