HM5425161B Datasheet, PDF (10/65 Pages) Elpida Memory – 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/ 16-Mword × 4-bit × 4-bank

HM5425161B, HM5425801B, HM5425401B Series
Pin Functions (1)
CLK, CLK (input pin): The CLK and the CLK are the master clock inputs. All inputs except DMs, DQSs
and DQs are referred to the cross point of the CLK rising edge and the V_REF level. When a read operation,
DQSs and DQs are referred to the cross point of the CLK and the CLK. When a write operation, DMs and
DQs are referred to the cross point of the DQS and the V_REF level. DQSs for write operation are referred to
the cross point of the CLK and the CLK.
CS (input pin): When CS is Low, commands and data can be input. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): These pins define operating commands (read, write, etc.) depending on
the combinations of their voltage levels. See "Command operation".
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross
point of the CLK rising edge and the V_REF level in a bank active command cycle. Column address (AY0 to
AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) is loaded
via the A0 to the A9 at the cross point of the CLK rising edge and the V_REF level in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a
write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If
A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged.
If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-
precharge function is disabled.
BA0/BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1,
bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank
1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is
selected.
CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh
commands are entered when the CKE is driven Low and exited when it resumes to High.
The CKE level must be kept for 1 CLK cycle (= t_CKEPW) at least, that is, if CKE changes at the cross point of
the CLK rising edge and the V_REF level with proper setup time t_IS, by the next CLK rising edge CKE level
must be kept with proper hold time t_IH.
Data Sheet E0086H20
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