HM5425161B Datasheet, PDF (16/65 Pages) Elpida Memory – 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/ 16-Mword × 4-bit × 4-bank

HM5425161B, HM5425801B, HM5425401B Series
Function Truth Table (2)
Current state
Activating*⁵
Active*⁶
CS RAS CAS WE Address
Command
Operation
H× × × ×
DESL
NOP
L H HH ×
NOP
NOP
L H HL ×
BST
ILLEGAL*¹²
L H L H BA, CA, A10 READ/READA ILLEGAL*¹²
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*¹²
L L H H BA, RA
ACTV
ILLEGAL*¹²
L L H L BA, A10
PRE, PALL
ILLEGAL*¹²
LL L× ×
ILLEGAL
H× × × ×
DESL
NOP
L H HH ×
NOP
NOP
L H HL ×
BST
ILLEGAL
L H L H BA, CA, A10 READ/READA Starting read
operation
L H L L BA, CA, A10 WRIT/WRITA Starting write
operation
Read*⁷
L L H H BA, RA
ACTV
ILLEGAL*¹²
L L H L BA, A10
PRE, PALL
Pre-charge
LL L× ×
ILLEGAL
H× × × ×
DESL
NOP
L H HH ×
NOP
NOP
L H HL ×
BST
BST
L H L H BA, CA, A10 READ/READA Interrupting burst
read operation to
start new read
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*¹⁴
L L H H BA, RA
ACTV
ILLEGAL*¹²
L L H L BA, A10
LL L× ×
PRE, PALL
Interrupting burst
read operation to
start pre-charge
ILLEGAL
Next state
Active
Active
—
—
—
—
—
—
Active
Active
Active
Read/READ
A
Write
recovering/
precharging
—
Idle
—
Active
Active
Active
Active
—
—
Precharging
—
Data Sheet E0086H20
16