HM5425161B Datasheet, PDF (18/65 Pages) Elpida Memory – 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/ 16-Mword × 4-bit × 4-bank

HM5425161B, HM5425801B, HM5425401B Series
Function Truth Table (4)
Current state CS RAS CAS WE Address
Command
Operation
Next state
Write with auto- H × × × ×
pre-charge*¹¹
DESL
NOP
Precharging
L H HH ×
NOP
NOP
Precharging
L H HL ×
BST
ILLEGAL
—
L H L H BA, CA, A10 READ/READA ILLEGAL*¹⁵
—
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL*¹⁵
—
L L H H BA, RA
ACTV
ILLEGAL*^{12, 15}
—
L L H L BA, A10
PRE, PALL
ILLEGAL*^{12, 15}
—
LL L× ×
ILLEGAL
—
Notes: 1. H: V_IH. L: V_IL. ×: V_IH or V_IL.
2. The DDR SDRAM is in "Precharging" state for t_RP after precharge command is issued.
3. The DDR SDRAM reachs "IDLE" state t_RP after precharge command is issued.
4. The DDR SDRAM is in "Refresh" state for t_RC after auto-refresh command is issued.
5. The DDR SDRAM is in "Activating" state for t_RCD after ACTV command is issued.
6. The DDR SDRAM is in "Active" state after "Activating" is completed.
7. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are
turned off.
8. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has
been output and DQ output circuits are turned off.
9. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
10. The DDR SDRAM is in "Write recovering" for t_WR after the last data are input.
11. The DDR SDRAM is in "Write with auto-precharge" until t_WR after the last data has been input.
12. This command may be issued for other banks, depending on the state of the banks.
13. All banks must be in "IDLE".
14. Before executing a write command to stop the preceding burst read operation, BST command must
be issued.
15. See ‘Read with Auto-Precharge Enabled, Write with Auto-Precharge Enable’ section.
Data Sheet E0086H20
18