HB52RF328GB-B Datasheet, PDF (12/16 Pages) Elpida Memory – 256MB Unbuffered SDRAM Micro DIMM

HB52RF328GB-B, HB52RD328GB-B
Relationship Between Frequency and Minimum Latency
Parameter
-75
Frequency (MHz)
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command (same
bank)
Precharge command to active command (same
bank)
Write recovery or data-in to precharge command
(same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lAPW
133
PC100
Symbol 7.5
3
9
6
3
Tdpl
2
2
Tsrx
1
Tdal
5
Self refresh exit to command input
lSEC
9
Precharge command to high impedance
(CL = 2)
(CL = 3)
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3)
lHZP
lHZP
lAPR
lEP
lEP
Troh 2
Troh 3
1
–1
–2
Column command to column command
lCCD
Tccd 1
Write command to data in latency
lWCD
Tdwd 0
DQMB to data in
lDID
Tdqm 0
DQMB to data out
lDOD
Tdqz 2
CKE to CK disable
lCLE
Tcke 1
Register set to active command
lRSA
Tmrd 1
/S to command disable
lCDD
0
Power down exit to command input
lPEC
1
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
-A6, -B6
100
10
2
7
5
2
2
2
1
4
7
2
3
1
–1
–2
1
0
0
2
1
1
0
1
Notes
1
= [lRAS+ lRP]
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Preliminary Data Sheet E0202H10 (Ver. 1.0)
12