E522.31_16 Datasheet, PDF (14/20 Pages) ELMOS Semiconductor AG – CHANNEL SWITCHED MODE CONSTANT CURRENT CONTROLLER

1 CHANNEL SWITCHED MODE CONSTANT CURRENT CONTROLLER
PRODUCTION DATA - JUL 21, 2016
E522.31/33
5.7 Outer Regulation Loop
The outer regulation loop provides control of the con-
verter in combination with the differential high-side
feedback amplifier at FBL and FBH. The failure amplifier
(named GM) provides the inner regulation loop refer-
ence voltage derived from CMP.
A typical compensation network required for optimized
operation is a network consisting of a capacitor to ref-
erence GND, parallel to a serial connection of a capaci-
tor and a resistor (see typical application diagram). Dur-
ing prototyping the compensation has to be verified for
the whole input voltage range, especially for the maxi-
mum duty cycle which occurs.
Under-voltage detection at FBL, FBH and CMP are pro-
vided to detect external failures like short-connections.
A soft-start mechanism is implemented to avoid exces-
sive input current flow. The soft-start startup time is
typically 7.5ms with PWDIM='1' to fully release convert-
er output power. A faster setting for softstart length
can be ordered, which leads to 3.75ms for a typical im-
plementation. The voltage slopes applied at CMP are ei-
ther typ. 200mV/ms (standard) or typ. 400mV/ms (fast).
Note that dimming at PWDIMx during softstart stretches this
delay (by approximately 1/dutycycle applied).
5.8 Over-Voltage Protection
The OVP (over voltage protection) Pins OVPIN and OVPO
provide a GND related output over-voltage protection.
The absolute voltage level of protection is defined by
the resistive divider with respect to the maximum volt-
age at pin OVPIN, connected from converter output
voltage to OVPIN and from OVPO to AGND. Recom-
mended resistive range is given in ROVPO.
If E522.3x is turned off or is dimmed, the connection
between OVPIN and OVPO is switched off, providing
high impedance to reduce current flow in over-voltage
protection. This feature also disconnects the DC path
between VIN and GND to save energy in sleep mode.
Note, that during PWDIM='0' the over-voltage protec-
tion is not available.
5.9 ERRB Output
ERRB open-drain output is used to set an error flag for • Open ADIM connection
peripheral components, e.g. microcontroller.
• Differential feedback FBH-FBL over-voltage ²⁾
The output drives the ERRB flag to AGND, if a failure is • PWDIM time-out (e.g. caused by short to GND)
detected. The following failure states are handled:
• Short in external dimming transistors ³⁾
• VSM or V3V3 under-voltage (e.g. short to GND)
• Over-voltage at OVPIN
• Junction over-temperature
• Open-load (detected by over-voltage protection) • Open AGND or PGND connection
• Open feedback connection at FBH or FBL
• DRVS under-voltage (below reset-threshold)
• Open current feedback at CSP
• ON voltage low (ON logically'0')
• FBH or FBL under-voltage detection
• Open RT input or out-of-range OSCIN signal
• Reversed feedback VFBH - VFBL < typ. -50mV
• Invalid frequency applied to OSCIN
• Continuous innerloop current limitation for typ.
>64ms ¹⁾
1) Error Flag is set for typ. 1s after detection, restarting the device afterwards.
2) Differential overvoltage at FBH/FBL is detected by CMP undervoltage detection to avoid sensitivity to distortions.
3) Differential voltage across FBH/FBL during dimming is supervised for a typ. threshold of 50mV after a delay of typ. 16µs fol-
lowing the falling edge of the PWDIM signal.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0085E.01
14/20