E522.31_16 Datasheet, PDF (13/20 Pages) ELMOS Semiconductor AG – CHANNEL SWITCHED MODE CONSTANT CURRENT CONTROLLER

1 CHANNEL SWITCHED MODE CONSTANT CURRENT CONTROLLER
PRODUCTION DATA - JUL 21, 2016
E522.31/33
5.4 Digital Dimming Logic
The PWM logic block controls the digital dimming of 0
to 100% at pin PWDIM. When PWM = '0' is applied to
pin PWDIM, E522.3x is set to hold state (high imped-
ant) for the regulation signal at CMPx. LGATE outputs
are set to match internal synchronization of PWM. Di-
rect control of external dimming transistors is not rec-
ommended.
At the falling edge of the PWM signal, dimming circuit is
checked for short circuit connections. To verify that the
external current is switched off, typ. 16µs after switch-
ing LGATE '0', internal control circuitry for short detec-
tion in the external dimming circuit is enabled. The
threshold for this detection is typ. 50mV V_FBH-FBL. With
the rising edge of V_PWDIMx this check is disabled again.
The PWM range of 0 to 100% with 0.1% resolution per-
mits LED brightness control of >1000:1 at a PWM fre-
quency of 400Hz.
Note, that during dimming the current in the exter-
nal inductor must settle to provide proper regulation.
Therefore the minimum dimming pulse width depends
on the external circuitry, input voltages and external
resonant frequencies, too.
Internal pull-up current to V3V3 makes the PWDIMx
pins suitable for open-drain / open-collector control
circuits. The voltage capability of V_VSM makes this input
5V/3.3V compatible as well.
5.5 Analog Dimming and Highside Sense
The ADIM section provides LED current adjustment, in-
dependent of digital dimming feature (e.g. binning or
initial current setting).
Voltages below typ. 0.16V are considered an open pin,
disabling the converter.
In the range of 0.24V to 2.4V the signal is accepted as
reference for regulation, divided by a factor of 6. To use
the internal reference voltage of typical 1.2V ( = 200mV
at V_FBH-FBL) solder this pin to V3V3.
The high side feedback FBH & FBL provides precise
measurement of the load current (e.g. LED current). In
any topology FBH must be connected to the positively
biased shunt resistor terminal.
Additionally, these pins are monitored for under-volt-
age to detect open pins or short-to-GND errors, disa-
bling the converter in case of detection. The under-
voltage threshold may be superseded by the VSM reset
generation.
Note that for SEPIC or Flyback topologies the output
must be precharged above the undervoltage threshold
at FBx to allow startup. For example the VSM regulator
is suitable to drive the output via a rectification device
or circuit.
5.6 Inner Current Regulation Loop
The Low side feedback CSxP and CSxN provides induc-
tor current measurement to the inner regulation loop
to control the pulse width of the CGATE output. Over-
Current protection is provided if the voltage at CSxP pin
exceeds 425mV relative to AGND, turning the accord-
ing CGATE driver off. For over-current limitation please
note , that the slope compensation may decrease the
actual current limitation for higher dutycycles.
CGATE output is designed to drive the gate of an exter-
nal true-logic-level N-channel FET with an average gate
current of 25mA at switching frequencies up to 660kHz
(in OSCIN synchronized operational mode).
The average current can be calculated by multiplication
of the operation frequency with the total gate charge
of the external FET. For example, for a transistor of
40nC gate-charge the maximum operational frequency
is 625kHz. Higher gate-charge leads to lower maximum
operational frequency (e.g. 100nC transistors are possi-
ble at a maximum frequency of 250kHz).
DRVS should be supplied by VSM (see chapter supply
for details). If DRVS is supplied externally, an maximum
average current of 40mA in each CGATE is possible. Take
additional power generated in E522.3x into account.
E522.3x device provide internal slope compensation
ramp generation. The slope can be scaled to match the
external circuitry by applying a resistor R_SLP between
the innerloop shunt R_SHUNT and pin CSxP.
For applications designed to work with higher dutycy-
cles than 50%, R_SLP should be choosen in the range from
typ. 330Ω to 2kΩ. Final resistor value should be defined
during prototyping of the complete application.
As a starting value for R_SLP in Boost configuration use
R_SLP
=
V
5
OUT^⋅R
e^−4⋅f
SHUNT
RT^⋅L
with f_RT = operating frequency set at RT
and L = inductance in Boost circuitry
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0085E.01
13/20