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GD25LQ256C Datasheet, PDF (36/68 Pages) ELM Electronics – 256M-bit Serial Flash
GD25LQ256CWIGx 1.8V Uniform Sector Dual and Quad Serial Flash
7.19. 32KB Block Erase (BE) (52H)
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The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and 3-byte address or 4-byte
address on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS#
must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte
address or 4-byte address on SI→ CS# goes high. The command sequence is shown in Figure20. CS# must be
driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE)
command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is
tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block
Protect (BP4, BP3, BP2, BP1 and BP0) bits (see Table1 & Table1a) is not executed.
Figure 20. 32KB Block Erase Sequence Diagram
CS#
SCLK
0123456789
29 30 31
SI
Command
24 Bits Address
52H
23 22
210
MSB
Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.
Figure 20a. 32KB Block Erase Sequence Diagram (QPI)
CS#
SCLK
IO0
IO1
IO2
IO3
012345 67
Command
52H A23-16 A12-8
20 16 12 8
A7-0
40
21 17 13 9 5 1
22 18 14 10 6 2
23 19 15 11 7 3
Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.
68 - 36
Rev.1.0