GD25LQ256C Datasheet, PDF(30/68 Page) ELM Electronics

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GD25LQ256C Datasheet, PDF (30/68 Pages) ELM Electronics – 256M-bit Serial Flash

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GD25LQ256CWIGx 1.8V Uniform Sector Dual and Quad Serial Flash

7.14. Quad I/O Word Fast Read (E7H)

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The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest

address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure15.

The first byte addressed can be at any location. The address is automatically incremented to the next higher

address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to

enable for the Quad I/O Word Fast read command.

Quad I/O Word Fast Read with âContinuous Read Modeâ

The Quad I/O Word Fast Read command can further reduce command overhead through setting the âContinuous

Read Modeâ bits (M7-0) after the input 3-byte address (A23-A0) or a 4-byte address (A31-A0). If the âContinuous

Read Modeâ bits (M5-4) = (1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and

then lowered) does not require the E7H command code. The command sequence is shown in followed Figure15.

If the âContinuous Read Modeâ bits (M5-4) do not equal to (1, 0), the next command requires the first E7H

command code, thus returning to normal operation. A âContinuous Read Modeâ Reset command can be used to

reset (M5-4) before issuing normal command.

Figure 15. Quad I/O Word Fast Read Sequence Diagram (M5-4 â (1, 0))

CS#

SCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SI(IO0)

Command

E7H

40404040

404040 4

SO(IO1)

51515151

515151 5

WP#(IO2)

62626262

626262 6

HOLD#(IO3)

73737373

737373 7

A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.

Figure 15a. Quad I/O Word Fast Read Sequence Diagram (M5-4 = (1, 0))

CS#