GD25LQ40XIGX Datasheet, PDF (25/59 Pages) ELM Technology Corporation – 1.8V Uniform Sector Dual and Quad Serial Flash

GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
Quad I/O Fast Read (EBH) in QPI mode
The Quad I/O Fast Read command is also supported in QPI mode. See Figure12b. In QPI mode, the number
of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range
application with different needs for either maximum Fast Read frequency or minimum data access latency.
Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either
4/6/8. In QPI mode, the “Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous
Read Mode” feature is also available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is
not available in QPI mode for Quad I/O Fast Read command. To perform a read operation with fixed data length
wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0CH) command must be used.
Figure 12b. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0) QPI)
CS#
SCLK
IO₀
IO₁
IO₂
IO₃
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Command
EBH
IOs switch from
Input to output
20 16 12 8 4 0 4 0 4 0 4 0 4
21 17 13 9 5 1 5 1 5 1 5 1 5
22 18 14 10 6 2 6 2 6 2 6 2 6
23 19 15 11 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0* _{Byte1 Byte2 Byte3}
*"Set Read Parameters"
Command (C0H) can
set the number of
dummy clocks
7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure13.
The first byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to
enable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =
(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require
the E7H command code. The command sequence is shown in followed Figure13. If the “Continuous Read
Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to
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