GD25LQ40XIGX Datasheet, PDF (23/59 Pages) ELM Technology Corporation – 1.8V Uniform Sector Dual and Quad Serial Flash

GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SI(IO0)
Command
BBH
6420642064206420
SO(IO1)
7531753175317531
A23-16
A15-8
A7-0
M7-0
CS#
SCLK ^{23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39}
SI(IO0) _{6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6}
SO(IO1)
7531753175317531 7
Byte1
Byte2
Byte3
Byte4
Figure 11a. Dual I/O Fast Read Sequence Diagram (M5-4 = (1, 0 ))
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
6420642064206420
CS#
SCLK
7531753175317531
A23-16
A15-8
A7-0
M7-0
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI(IO0) _{6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6}
SO(IO1)
7531753175317531 7
Byte1
Byte2
Byte3
Byte4
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock
by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed
Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be
set to enable for the Quad I/O Fast read command.
59 - 23
Rev.1.0