DRPIC1655X Datasheet, PDF (6/8 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
Speed
grade
Logic Cells
F_max
CYCLONE
-6
921
111 MHz
CYCLONE
-6
923
107 MHz
STRATIX
-5
922
114 MHz
STRATIX II
-3
823
189 MHz
STRATIX GX -5
922
116 MHz
APEX II
-5
1131
94 MHz
APEX20KC
-7
1131
81 MHz
APEX20KE
-1
1131
70 MHz
APEX20K
-1
1131
41 MHz
ACEX1K
-1
1150
64 MHz
FLEX10KE
-1
1150
59 MHz
Core performance in ALTERA® devices
Area utilized by the each unit of DRPIC1655X
core in vendor specific technologies is
summarized in table below.
Component
AREA
[LC]
[FFs]
CPU*
711
285
Timer 0
60
29
Watchdog Timer
55
38
I/O Ports
96
64
Total area
922
416
*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack,
Extended interrupt controller, External INT pin Interrupt Controller,
Extended Interrupt controller, 512 B of RAM 8kW of program memory
Core components area utilization - CYCLONE
IMPROVEMENT
Most instruction of DRPIC1655X is
executed within 1 CLK period, except program
branches that require 2 CLK periods. The
table below shows sample instructions
execution times:
Mnemonic DRPIC1655X
operands (CLK cycles)
PIC16C554
(CLK cycles)
Impr.
ADDWF
1
4
4
ANDWF
1
4
4
RLF
1
4
4
BCF
DECFSZ
INCFSZ
BTFSC
BTFSS
1
1(2)¹
1(2)¹
1(2)¹
1(2)¹
4
4
4(8)¹
4
4(8)¹
4
4(8)¹
4
4(8)¹
4
CALL
2
8
4
GOTO
2
8
4
RETFIE
2
8
4
RETLW
2
8
4
RETURN
2
8
4
1 _{number of clock in case when result of operation is 0.}
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.