DRPIC1655X Datasheet, PDF (4/8 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

BLOCK DIAGRAM
ALU – Arithmetic Logic Unit performs
arithmetic and logic operations during
execution of an instruction. This module
contains work register (W) and Status register.
Control Unit – It performs the core
synchronization and data flow control. This
module manages execution of all instructions.
Performs decode and control functions for all
other blocks. It contains program counter (PC)
and hardware stack.
Hardware Stack – it’s a configurable
hardware stack. The stack space is not a part
of either program or data space and the stack
pointer is not readable or writable. The PC is
pushed onto the stack when CALL instruction
is executed or an interrupt causes a branch.
The stack is popped while RETURN, RETFIE
and RETLW instruction execution. The stack
operates as a circular buffer. This means that
after the stack has been pushed eight times,
the ninth push overwrites the value that was
stored from the first push.
RAM Controller – It performs interface
functions between Data memory and
DRPIC1655X internal logic. It assures correct
Data Memory addressing and data transfers.
The DRPIC1655X supports two addressing
modes: direct or indirect. In Direct Addressing
the 9-bit direct address is computed from
RP(1:0) bits (STATUS) and 7 least significant
bits of instruction word.
Indirect addressing is possible by using the
INDF register. Any instruction using INDF
register actually accesses data pointed to by
the file select register FSR. Reading INDF
register indirectly will produce 00h. Writing to
the INDF register indirectly results in a no-
operation. An effective 9-bit address is
obtained by concatenating the IRP bit
(STATUS) and the 8-bit FSR register.
Interrupt Controller – Interrupt Controller
module is responsible for interrupt manage
system for the external and internal interrupt
sources. It contains interrupt related register
called INTCON. There are three interrupt
sources:
♦ External interrupt INT
♦ TMR0 overflow interrupt
♦ PORTB change interrupt (pins B7:B4)
The interrupt control register INTCON records
individual interrupt requests in flag bits.
A global interrupt enable bit, GIE enables all
unmasked interrupts. Each interrupt source
has an individual enable bit, which can enable
or disable corresponding interrupt.
When an interrupt is responded to, the GIE is
cleared to disable any further interrupt, the
return address is pushed into the stack and
the PC is loaded with 0004h. The interrupt flag
bits must be cleared in software before re-
enabling interrupts.
clk
por
Hardware
Stack
ALU
mclr
sleep
prgdata
prgaddr
Control
Unit
intr
Interrupt
Controller
t0cki
Timer 0
clkwdt
docddatai
docddatao
docdclk
prgdatao
prgwe
Watchdog
Timer
DoCD^TM
Debugger
RAM
Controller
I/O
Ports
ramdatai
ramdatao
rdaddr
wraddr
ramwe
ramoe
sfrdatai
sfrrdaddr
sfrwraddr
sfrwe
sfroe
portai
portbi
portci
portdi
portao
portbo
portco
portdo
trisa
trisb
trisc
trisd
Timer 0 – Main system’s timer and prescaler.
This timer operates in two modes: 8-bit timer
or 8-bit counter. In the “timer mode”, timer
registers are incremented every 4 CLK
periods. When the prescaler is assigned into
the TIMER prescale ration can be divided by
2, 4 .. 256. In the “counter mode” the timer
register is incremented every falling or rising
edge of T0CKI pin, dependent on T0SE bit in
OPTION register.
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