DRPIC1655X Datasheet, PDF (2/8 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

PERIPHERALS
● Four 8 bit I/O ports
○ Four 8-bit corresponding TRIS registers
○ Interrupt feature on PORTB(7:4) change
● Timer 0
○ 8-bit timer/counter
○ Readable and Writable
○ 8-bit software programmable prescaler
○ Internal or external clock select
○ Interrupt generation on timer overflow
○ Edge select for external clock
● Watchdog Timer
○ Configurable Time out period
○ 7-bit software programmable prescaler
○ Dedicated independent Watchdog Clock input
● Extended Interrupt Controller
○ Three individually maskable Interrupt sources
○ External interrupt INT
○ Timer Overflow interrupt
○ Port B[7:4] change interrupt
● DoCD™ debug unit
○ Processor execution control
○ Run
○ Halt
○ Step into instruction
○ Skip instruction
○ Read-write all processor contents
○ Program Counter (PC)
○ Program Memory
○ Data Memory
○ Special Function Registers (SFRs)
○ Hardware Stack and Stack Pointer
○ Hardware execution breakpoints
○ Program Memory
○ Data Memory
○ Special Function Registers (SFRs)
○ Hardware breakpoints activated at a certain
○ Program address (PC)
○ Address by any write into memory
○ Address by any read from memory
○ Address by write into memory a required data
○ Address by read from memory a required data
○ Three wire communication interface
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench
environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
CONFIGURATION
The following parameters of the DRPIC1655X
core can be easy adjusted to requirements of
dedicated application and technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
•
Number
levels
of
hardware
stack
• Memories type
• SLEEP mode
• WATCHDOG Timer
• Timer system
• Interrupt system
• PORTS A,B,C,D
• DoCD^TM Debug Unit
- 1-16
- default 8
- synchronous
- asynchronous
- used
- unused
- used / width
- unused
- used
- unused
- used
- unused
- used
- unused
- used
- unused
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