DRPIC1655X Datasheet, PDF (3/8 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC
implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time
restriction except One Year license where
time of use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
clkwdt
input Global clock
input Watchdog clock
por
mclr
prgdata[13:0]
input
input
input
Global reset Power On Reset
User reset
Data bus from program memory
ramdatai[7:0]
sfrdatai[7:0]
intr
input
input
input
Data bus from int. data memory
Data bus from External SFR regs.
External interrupt
t0cki
portxi[7:0]
docddatai
input
input
input
Timer 0 input
Port A, B, C, D input
DoCD^TM Debugger input
prgaddr[15:0]
ramdatao[7:0]
rdaddr[14:0]
output Program memory address bus
output Data bus for internal data memory
output RAM read address bus
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wraddr[14:0]
ramwe
ramoe
sfrwraddr[3:0]
sfrrdaddr[14:0]
sfrwe
sfroe
sleep
portxo[7:0]
trisx[7:0]
docddatao
docdclk
prgdatao[13:0]
prgwe
output RAM write address bus
output Data memory write
output Data memory output enable
output External SFR’s write address bus
output External SFR’s read address bus
output External SFR’s write enable
output External SFR’s output enable
output Sleep signal
output Port A, B, C, D outputs
output Ports A, B, C, D data direction pins
output DoCD^TM Debugger data output
output DoCD^TM Clock line
output Program Memory data output
output Program Memory write enable
SYMBOL
clk
clkwdt
por
mclr
prgdata(13:0) prgaddr(15:0)
ramdatai(7:0)
sfrdatai(7:0)
intr
ramdatao(7:0)
rdaddr(14:0)
wraddr(14:0)
ramwe
ramoe
sfrrdaddr(3:0)
sfrwraddr(3:0)
sfrwe
sfroe
sleep
t0cki
portai(7:0)
portbi(7:0)
portci(7:0)
portdi(7:0)
portao(7:0)
portbo(7:0)
portco(7:0)
portdo(7:0)
trisa(7:0)
trisb(7:0)
trisc(7:0)
trisd(7:0)
docddatai
DoCD^TM Interface
docddatao
docdclk
prgdatao(13:0)
prgwe
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