DRPIC1655X Datasheet, PDF (1/8 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

DRPIC1655X
High Performance Configurable
8-bit RISC Microcontroller
ver 2.15
OVERVIEW
The DRPIC1655X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core,
dedicated for operation with fast (typically on-
chip) dual ported memory. The core has been
designed with a special concern about low
power consumption.
DRPIC1655X soft core is software-
compatible with the industry standard
PIC16C554 and PIC16C558. It implements an
enhanced Harvard architecture (i.e.
separate instruction and data memories) with
independent address and data buses. The 14
bit program memory and 8-bit dual port data
memory allow instruction fetch and data
operations to occur simultaneously. The
advantage of this architecture is that
instruction fetch and memory transfers can be
overlapped by multi stage pipeline, so that the
next instruction can be fetched from program
memory while the current instruction is
executed with data from the data memory.
The DRPIC1655X architecture is 4 times
faster compared to standard architecture. So
most instructions are executed within 1
system clock period, except the instructions
which directly operates on program counter
PC (GOTO, CALL, RETURN), this situation
require the pipeline to be cleared and
subsequently refilled. This operation takes
additional one clock cycle.
The DRPIC1655X Microcontroller fits
perfectly in applications ranging from high-
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speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode make this IP perfect
for applications where power consumption is
critical.
DRPIC1655X is delivered with fully
automated testbench and complete set of
tests allowing easy package validation at
each stage of SoC design flow
CPU FEATURES
● Software compatible with industry standard
PIC16C55X
● Pipelined Harvard architecture 4 times
faster compared to original implementation
● 35 instructions
● 14 bit wide instruction word
● Up to 32 K bytes of internal Data Memory
● Up to 64K bytes of Program Memory
● Configurable hardware stack
● Power saving SLEEP mode
● Fully synthesizable, static synchronous
design with no internal tri-states
● Technology independent HDL Source
Code
● 1.4 GHz virtual clock frequency in a 0.18u
technological process
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