DS1495 Datasheet, PDF (9/19 Pages) Dallas Semiconductor – RAMified Real Time Clock

DS1495/DS1497
UPDATE CYCLE
The DS1495/DS1497 executes an update cycle once
per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user
copy of the double buffered time, calendar, and alarm
bytes is frozen and will not update as the time incre-
ments. However, the time countdown chain continues
to update the internal copy of the buffer. This feature al-
lows time to maintain accuracy independent of reading
or writing the time, calendar, and alarm buffers and also
guarantees that time and calendar information is con-
sistent. The update cycle also compares each alarm
byte with the corresponding time byte and issues an
alarm if a match or if a “don’t care” code is present in all
three positions.
There are three methods that can handle access of the
real-time clock that avoid any possibility of accessing in-
consistent time and calendar data. The first method
uses the update-ended interrupt. If enabled, an inter-
rupt occurs after every update cycle that indicates that
over 999 ms are available to read valid time and date in-
formation. If this interrupt is used, the IRQF bit in Regis-
ter C should be cleared before leaving the interrupt rou-
tine.
A second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in prog-
ress. The UIP bit will pulse once per second. After the
UIP bit goes high, the update transfer occurs 244 µs lat-
er. If a low is read on the UIP bit, the user has at least
244 µs before the time/calendar data will be changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244 µs.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in Register
C (see Figure 3). Periodic interrupts that occur at a rate
of greater than t_BUC allow valid time and date informa-
tion to be reached at each occurrence of the periodic in-
terrupt. The reads should be complete within
(t_PI/2+t_BUC) to ensure that data is not read during the up-
date cycle.
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 4
UIP BIT IN
REGISTER A
UF BIT IN
REGISTER C
PF BIT IN
REGISTER C
t
PI
t_PI = Periodic interrupt time interval per Table 1.
t_BUC = Delay time before update cycle = 244 µs.
t _BUC
t _PI/2
t _PI/2
020894 9/19