DS1495 Datasheet, PDF (10/19 Pages) Dallas Semiconductor – RAMified Real Time Clock

DS1495/DS1497
REGISTERS
The DS1495/DS1497 has four control registers which
are accessible at all times, even during the update
cycle.
REGISTER A
MSB
BIT 7 BIT 6
UIP DV2
BIT 5
DV1
BIT 4
DV0
BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
LSB
BIT 0
RS0
UIP - The Update In Progress (UIP) bit is a status flag
that can be monitored. When the UIP bit is a one, the
update transfer will soon occur. When UIP is a zero, the
update transfer will not occur for at least 244 µs. The
time, calendar, and alarm information in RAM is fully
available for access when the UIP bit is zero. The UIP
bit is read only. Writing the SET bit in Register B to a one
inhibits any update transfer and clears the UIP status
bit.
DV2, DV1, DV0 - These three bits are used to turn the
oscillator on or off and to reset the countdown chain. A
pattern of 010 is the only combination of bits that will turn
the oscillator on and allow the RTC to keep time. A pat-
tern of 11X will enable the oscillator but holds the count-
down chain in reset. The next update will occur at 500
ms after a pattern of 010 is written to DV2, DV1, and
DV0.
RS3, RS2, RS1, RS0 - These four rate-selection bits se-
lect one of the 13 taps on the 15-stage divider or disable
the divider output. The tap selected can be used to gen-
erate an output square wave (SQW pin) and/or a period-
ic interrupt. The user can do one of the following
1. Enable the interrupt with the PIE bit;
2. Enable the SQW output pin with the SQWE bit;
3. Enable both at the same time and the same rate; or
4. Enable neither.
Table 2 lists the periodic interrupt rates and the square
wave frequencies that can be chosen with the RS bits.
REGISTER B
MSB
BIT 7 BIT 6
SET PIE
BIT 5
AIE
BIT 4
UIE
BIT 3
SQWE
BIT 2
DM
BIT 1
24/12
LSB
BIT 0
DSE
SET - When the SET bit is a zero, the update transfer
functions normally by advancing the counts once per
second. When the SET bit is written to a one, any update
transfer is inhibited and the program can initialize the
time and calendar bytes without an update occurring in
the midst of initializing. Read cycles can be executed in
a similar manner. SET is a read/write bit that is not modi-
fied by internal functions of the DS1495/DS1497.
PIE - The Periodic Interrupt Enable bit is a read/write bit
which allows the Periodic Interrupt Flag (PF) bit in Reg-
ister C to drive the IRQ pin low. When the PIE bit is set to
one, periodic interrupts are generated by driving the
IRQ pin low at a rate specified by the RS3-RS0 bits of
Register A. A zero in the PIE bit blocks the IRQ output
from being driven by a periodic interrupt, but the Period-
ic Flag (PF) bit is still set at the periodic rate. PIE is not
modified by any internal DS1495/DS1497 functions but
is cleared by the hardware RESET signal.
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write
bit which, when set to a one, permits the Alarm Flag (AF)
bit in register C to assert IRQ. An alarm interrupt occurs
for each second that the three time bytes equal the three
alarm bytes including a don’t care alarm code of binary
11XXXXXX. When the AIE bit is set to zero, the AF bit
does not initiate the IRQ signal. The internal functions of
the DS1495/DS1497 do not affect the AIE bit but is
cleared by RESET.
UIE - The Update Ended Interrupt Enable (UIE) bit is a
read/write bit that enables the Update Ended Flag (UF)
bit in Register C to assert IRQ. The SET bit going high or
the RESET pin going low clears the UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit is
set to a one, a square wave signal at the frequency set
by the rate-selection bits RS3 through RS0 is driven out
on a SQW pin. When the SQWE bit is set to zero, the
SQW pin is held low. SQWE is a read/write bit and is
cleared by RESET.
DM - The Data Mode (DM) bit indicates whether time
and calendar information is in binary or BCD format.
The DM bit is set by the program to the appropriate for-
mat and can be read as required. This bit is not modified
by internal functions. A one in DM signifies binary data
while a zero in DM specifies Binary Coded Decimal
(BCD) data.
24/12 - The 24/12 control bit establishes the format of
the hours byte. A one indicates the 24-hour mode and a
zero indicates the 12-hour mode. This bit is read/write.
020894 10/19