DS12B887 Datasheet, PDF (8/16 Pages) Dallas Semiconductor – Real Time Clock

DS12B887
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
UIP BIT IN
REGISTER A
UF BIT IN
REGISTER B
PF BIT IN
REGISTER C
t_PI
t_PI = Periodic interrupt time interval per Table 1.
t_BUC = Delay time before update cycle = 244 µs.
t_BUC
t_PI/2
t_PI/2
REGISTERS
The DS12B887 has four control registers which are
accessible at all times, even during the update cycle.
REGISTER A
MSB
BIT 7 BIT 6 BIT 5
UIP DV2 DV1
BIT 4
DV0
BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
LSB
BIT 0
RS0
UIP
The Update In Progress (UIP) bit is a status flag that can
be monitored. When the UIP bit is a one, the update
transfer will soon occur. When UIP is a zero, the update
transfer will not occur for at least 244 µs. The time, cal-
endar, and alarm information in RAM is fully available
for access when the UIP bit is zero. The UIP bit is read
only. Writing the SET bit in Register B to a one inhibits
any update transfer and clears the UIP status bit.
DV0, DV1, DV2
These three bits are used to turn the oscillator on or off
and to reset the countdown chain. A pattern of 010 is the
only combination of bits that will turn the oscillator on
and allow the RTC to keep time. A pattern of 11X will
enable the oscillator but holds the countdown chain in
reset. The next update will occur at 500 ms after a pat-
tern of 010 is written to DV0, DV1, and DV2.
RS3, RS2, RS1, RS0
These four rate-selection bits select one of the 13 taps
on the 15-stage divider or disable the divider output.
The tap selected can be used to generate an output
square wave (SQW pin) and/or a periodic interrupt. The
user can do one of the following:
1. Enable the interrupt with the PIE bit;
2. Enable the SQW output pin with the SQWE bit;
3. Enable both at the same time and the same rate; or
4. Enable neither.
Table 1 lists the periodic interrupt rates and the square
wave frequencies that can be chosen with the RS bits.
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