DS12B887 Datasheet, PDF (6/16 Pages) Dallas Semiconductor – Real Time Clock

DS12B887
TIME, CALENDAR AND ALARM DATA MODES Table 2
ADDRESS
LOCATION
FUNCTION
DECIMAL
RANGE
RANGE
BINARY DATA MODE
BCD DATA MODE
0
Seconds
0-59
00-3B
00-59
1
Seconds Alarm
0-59
00-3B
00-59
2
Minutes
0-59
00-3B
00-59
3
Minutes Alarm
0-59
00-3B
00-59
4
Hours-12-hr Mode
1-12
01-0C AM, 81-8C PM
01-12AM,81-92PM
Hours-24-hr Mode
0-23
00-17
00-23
5
Hours Alarm-12-hr
1-12
01-0C AM, 81-8C PM
01-12AM,81-92PM
Hours Alarm-24-hr
0-23
00-17
00-23
6
Day of the Week
Sunday = 1
1-7
01-07
01-07
7
Date of the Month
1-31
01-1F
01-31
8
Month
1-12
01-0C
01-12
9
Year
0-99
00-63
00-99
NONVOLATILE RAM
The 114 general purpose nonvolatile RAM bytes are not
dedicated to any special function within the DS12B887.
They can be used by the processor program as nonvol-
atile memory and are fully available during the update
cycle.
INTERRUPTS
The RTC plus RAM includes three separate, fully auto-
matic sources of interrupt for a processor. The alarm
interrupt can be programmed to occur at rates from
once per second to once per day. The periodic interrupt
can be selected for rates from 500 ms to 122 µs. The
update-ended interrupt can be used to indicate to the
program that an update cycle is complete. Each of
these independent interrupt conditions is described in
greater detail in other sections of this text.
The processor program can select which interrupts, if
any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-
enable bit permits that interrupt to be initiated when the
event occurs. A zero in an interrupt-enable bit prohibits
the IRQ pin from being asserted from that interrupt
condition. If an interrupt flag is already set when an
interrupt is enabled, IRQ is immediately set at an active
level, although the interrupt initiating the event may
have occurred much earlier. As a result, there are cases
where the program should clear such earlier initiated
interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C. These flag bits are set inde-
pendent of the state of the corresponding enable bit in
Register B. The flag bit can be used in a polling mode
without enabling the corresponding enable bits. The
interrupt flag bit is a status bit which software can
interrogate as necessary. When a flag is set, an indica-
tion is given to software that an interrupt event has
occurred since the flag bit was last read; however, care
should be taken when using the flag bits as they are
cleared each time Register C is read. Double latching is
included with Register C so that bits which are set
remain stable throughout the read cycle. All bits which
are set (high) are cleared when read and new interrupts
which are pending during the read cycle are held until
after the cycle is completed. One, two, or three bits can
be set when reading Register C. Each utilized flag bit
should be examined when read to ensure that no inter-
rupts a re lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt flag bit is set and the corre-
sponding interrupt enable bit is also set, the IRQ pin is
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