DS12B887 Datasheet, PDF (10/16 Pages) Dallas Semiconductor – Real Time Clock

DS12B887
PF
The Periodic Interrupt Flag (PF) is a read-only bit which
is set to a one when an edge is detected on the selected
tap of the divider chain. The RS3 through RS0 bits
establish the periodic rate. PF is set to a one indepen-
dent of the state of the PIE bit. When both PF and PIE
are ones, the IRQ signal is active and will set the IRQF
bit. The PF bit is cleared by a software read of Register
C.
BIT 0 THROUGH BIT 3
These are unused bits of the status Register C. These
bits always read zero and cannot be written.
REGISTER D
MSB
BIT 7 BIT 6 BIT 5
VRT
0
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
AF
A one in the Alarm Interrupt Flag (AF) bit indicates that
the current time has matched the alarm time. If the AIE
bit is also a one, the IRQ pin will go low and a one will
appear in the IRQF bit. A read of Register C will clear
AF.
VRT
The Valid RAM and Time (VRT) bit is set to the one state
by Dallas Semiconductor prior to shipment. This bit is
not writable and should always be a one when read. If a
zero is ever present, an exhausted internal lithium
energy source is indicated and both the contents of the
RTC data and RAM data are questionable.
UF
The Update Ended Interrupt Flag (UF) bit is set after
each update cycle. When the UIE bit is set to one, the
one in UF causes the IRQF bit to be a one which will
assert the IRQ pin. UF is cleared by reading Register C.
BIT 6 THROUGH BIT 0
The remaining bits of Register D are not usable. They
cannot be written and, when read, they will always read
zero.
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