DS12B887 Datasheet, PDF (4/16 Pages) Dallas Semiconductor – Real Time Clock

DS12B887
AD0-AD7 (Multiplexed Bidirectional Address/Data
Bus) - Multiplexed buses save pins because address
information and data information time share the same
signal paths. The addresses are present during the first
portion of the bus cycle and the same pins and signal
paths are used for data in the second portion of the cycle.
Address/data multiplexing does not slow the access time
of the DS12B887 since the bus change from address to
data occurs during the internal RAM access time.
Addresses must be valid prior to the falling edge of AS/
ALE, at which time the DS12B887 latches the address
from AD0 to AD6. Valid write data must be present and
held stable during the latter portion of the DS or WR
pulses. In a read cycle the DS12B887 outputs 8 bits of
data during the latter portion of the DS or RD pulses. The
read cycle is terminated and the bus returns to a high
impedance state as RD transitions high.
AS (Address Strobe Input) - A positive going address
strobe pulse serves to demultiplex the bus. The falling
edge of AS/ALE causes the address to be latched within
the DS12B887.
DS (Data Strobe or Read Input) - The DS pin is called
Read(RD). RD identifies the time period when the
DS12B887 drives the bus with read data. The RD signal
is the same definition as the Output Enable (OE) signal
on a typical memory.
R/W (Read/Write Input)-The R/W signal is an active low
signal called WR. In this mode the R/W pin has the
same meaning as the Write Enable signal (WE) on
generic RAMs.
CS (Chip Select Input) - The Chip Select signal must
be asserted low for a bus cycle in the DS12B887 to be
accessed. CS must be kept in the active state during
RD and WR. Bus cycles which take place without
asserting CS will latch addresses but no access will
occur. When V_CC is below 4.25 volts, the DS12B887
internally inhibits access cycles by internally disabling
the CS input. This action protects both the real time
clock data and RAM data during power outages.
IRQ (Interrupt Request Output) - The IRQ pin is an
active low output of the DS12B887 that can be used as an
interrupt input to a processor. The IRQ output remains
low as long as the status bit causing the interrupt is pres-
ent and the corresponding interrupt-enable bit is set. To
clear the IRQ pin the processor program normally reads
the C register.
When no interrupt conditions are present, the IRQ level is
in the high impedance state. Multiple interrupting devices
can be connected to an IRQ bus. The IRQ bus is an open
drain output and requires an external pull-up resistor.
RCLR (RAM Clear) - The RCLR pin is used to clear (set
to logic 1) all 114 bytes of general-purpose RAM but
does not affect the RAM associated with the real time
clock. In order to clear the RAM, RCLR must be forced
to an input logic of (-0.3 to +0.8 volts) when V_CC is ap-
plied. The RCLR function is designed to be used via hu-
man interface (shorting to ground manually or by switch)
and not to be driven with external buffers. This pin is in-
ternally pulled up. Do not use an external pull-up resistor
on this pin.
ADDRESS MAP
The address map of the DS12B887 is shown in Figure 2.
The address map consists of 114 bytes of user RAM, 10
bytes of RAM that contain the RTC time, calendar, and
alarm data, and four bytes which are used for control
and status. All 128 bytes can be directly written or read
except for the following:
1. Registers C and D are read-only.
2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
The contents of four registers (A,B,C, and D) are
described in the “Registers” section.
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