DS1220AB Datasheet, PDF (7/9 Pages) Dallas Semiconductor – 16k Nonvolatile SRAM

POWER-DOWN/POWER-UP CONDITION
DS1220AB/AD
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
CE at V_IH before Power-Down
t_PD
V_CC slew from V_TP to 0v
t_F
V_CC slew from 0_V to V_TP
t_R
CE at V_IH after Power-Up
t_REC
MIN
0
300
300
2
TYP
(t_A: See Note 10)
MAX UNITS NOTES
µs
11
µs
µs
125 ms
PARAMETER
Expected Data Retention Time
(T_A =25°C)
SYMBOL MIN TYP MAX UNITS NOTES
t_DR
10
years
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = V_IH or V_IL. If OE = V_IH during write cycle, the output buffers remain in a high-impedance state.
3. t_WP is specified as the logical AND of CE and WE . t_WP is measured from the latter of CE or CE
going low to the earlier of CE or WE going high.
4. t_DS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
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