DS1258Y Datasheet, PDF (6/8 Pages) Dallas Semiconductor – 128k x 16 Nonvolatile SRAM

POWER-DOWN/POWER-UP CONDITION
DS1258Y/AB
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
CEU , CEL at V_IH before Power-Down
t_PD
V_CC slew from V_TP to 0V
t_F
V_CC slew from 0V to V_TP
t_R
CEU , CEL at V_IH after Power-Up
t_REC
MIN
0
300
300
2
TYP
(t_A: See Note 10)
MAX UNITS NOTES
ms
11
ms
ms
125
ms
PARAMETER
Expected Data Retention Time
SYMBOL MIN TYP
t_DR
10
MAX
(t_A =+25°C)
UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1) WE is high for a Read Cycle.
2) OE = V_IH or V_IL. If OE = V_IH during write cycle, the output buffers remain in a high impedance state.
3) t_WP is specified as the logical AND of CEU or CEL and WE . t_WP is measured from the latter of CEU ,
CEL or WE going low to the earlier of CEU , CEL or WE going high.
4) t_DS is measured from the earlier of CEU or CEL or WE going high.
5) These parameters are sampled with a 5pF load and are not 100% tested.
6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in
the output buffers remain in a high impedance state during this period.
7) If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the
output buffers remain in high impedance state during this period.
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