DS1258Y Datasheet, PDF (2/8 Pages) Dallas Semiconductor – 128k x 16 Nonvolatile SRAM

DS1258Y/AB
READ MODE
The DS1258 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and either/both
of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable) is active (low). The unique
address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is
accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If
CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is
inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU
and CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to
the 16 data output drivers within t_ACC (Access Time) after the last address input signal is stable, providing
that CEU , CEL and OE access times are also satisfied. If CEU , CEL , and OE access times are not
satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is
either t_CO for CEU , CEL , or t_OE for OE rather than address access.
WRITE MODE
The DS1258 devices execute a write cycle whenever WE and either/both of CEU or CEL are active (low)
after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines
which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or
part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of
the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the
addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word
is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE . All
address inputs must be kept valid throughout the write cycle. WE must return to the high state for a
minimum recovery time (t_WR) before another cycle can be initiated. The OE control signal should be kept
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled
( CEU and/or CEL , and OE active) then WE will disable the outputs in t_ODW from its falling edge.
READ/WRITE FUNCTION Table 1
V_CC
OE
WE
CEL
CEU CURRENT
H
H
X
X
I_CCO
L
H
L
L
L
H
L
H
I_CCO
L
H
H
L
X
L
L
L
X
L
L
H
I_CCO
X
L
H
L
X
X
H
H
I_CCS
DQ0-DQ7
High-Z
Output
Output
High-Z
Input
Input
High-Z
High-Z
DQ8-DQ15
High-Z
Output
High-Z
Output
Input
High-Z
Input
High-Z
CYCLE
PERFORMED
Output Disabled
Read Cycle
Write Cycle
Output Disabled
DATA RETENTION MODE
The DS1258AB provides full functional capability for V_CC greater than 4.75V, and write protects by
4.5V. The DS1258Y provides full functional capability for V_CC greater than 4.5V and write protects by
4.25V. Data is maintained in the absence of V_CC without any additional support circuitry. The NV static
RAMs constantly monitor V_CC. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V_CC falls
below approximately 3.0V, a power switching circuit connects the lithium energy source to RAM to
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