DS5002FP_1 Datasheet, PDF (4/29 Pages) Dallas Semiconductor – Secure Microprocessor Chip

DS5002FP
PIN DESCRIPTION
PIN
DESCRIPTION
11, 9, 7, 5, 1,
79, 77, 75
P0.0 - P0.7. General purpose I/O Port 0. This port is open-drain and can not drive a logic 1. It requires
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in this mode, it
does not require pullups.
15, 17, 19, 21, P1.0 - P1.7. General purpose I/O Port 1.
25, 27, 29, 31
49, 50, 51, 56, P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the expanded address bus.
58, 60, 64, 66
36
P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART.
This pin should NOT be connected directly to a PC COM port.
38
P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART.
This pin should NOT be connected directly to a PC COM port.
39
P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0.
40
P3.3 INT1 . General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1.
41
P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input.
44
P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input.
45
P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation.
46
P3.7 RD . General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation.
34
RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled
down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is not
needed and is NOT recommended.
70
ALE - Address Latch Enable. Used to de-multiplex the multiplexed expanded address/data bus on port 0.
This pin is normally connected to the clock input on a ’373 type transparent latch.
47, 48
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an
inverting amplifier and XTAL2 is the output.
52
GND - Logic ground.
13
V_CC - +5V
12
V_CCO - V_CC Output. This is switched between V_CC and V_LI by internal circuits based on the level of V_CC.
When power is above the lithium input, power will be drawn from V_CC. The lithium cell remains isolated
from a load. When V_CC is below V_LI, the V_CCO switches to the V_LI source. V_CCO should be connected to
the V_CC pin of an SRAM.
54
V_LI - Lithium Voltage Input. Connect to a lithium cell greater than V_LImin and no greater than V_Limax as
shown in the electrical specifications. Nominal value is +3V.
16, 8, 18, 80,
76, 4, 6, 20,
24, 26, 28, 30,
33, 35, 37
BA14 - 0. Byte-wide address bus bits 14-0. This bus is combined with the non–multiplexed data bus
(BD7-0) to access NVSRAM. Decoding is performed using CE1 through CE4 . Therefore, BA15 is not
actually needed. Read/write access is controlled by R/ W . BA14-0 connect directly to an 8k, 32k, or 128k
SRAM. If an 8k RAM is used, BA13 and BA14 will be unconnected. If a 128k SRAM is used, the micro
converts CE2 and CE3 to serve as A16 and A15 respectively.
71, 69, 67, 65, BD7 - 0. Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the non-multiplexed
61, 59, 57, 55 _{address bus (BA14-0) to access NV SRAM. Decoding is performed on CE1 and CE2 . Read/write access}
is controlled by R/ W . BD7-0 connect directly to an SRAM, and optionally to a real-time clock or other
peripheral.
10
R/ W - Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It is
controlled by the memory map and partition. The blocks selected as program (ROM) will be write-
protected.
74
CE1 - Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-wide bus. It
connects to the chip enable input of one SRAM. CE1 is lithium-backed. It will remain in a logic high
inactive state when V_CC falls below V_LI.
2
CE2 - Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It connects
to the chip enable input of one SRAM. When MSEL=0, the micro converts CE2 into A16 for a 128k x 8
SRAM. CE2 is lithium-backed and will remain at a logic high when V_CC falls below V_LI.
PIN
DESCRIPTION
63
CE3 - Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It connects to
the chip enable input of one SRAM. When MSEL=0, the micro converts CE3 into A15 for a 128k x 8
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