DS5002FP_1 Datasheet, PDF (23/29 Pages) Dallas Semiconductor – Secure Microprocessor Chip

AC CHARACTERISTICS (cont’d)
BYTEWIDE ADDRESS/DATA BUS TIMING
#
PARAMETER
SYMBOL
40 Delay to Byte-wide Address Valid from
CE1 , CE2 or CE1N Low During Opcode
t_CE1LPA
Fetch
41 _{Pulse Width of CE 1-4, PE 1-4 or CE1N}
t_CEPW
42 _{Byte-wide Address Hold After CE1 , CE2}
t_CE1HPA
or CE1N High During Opcode Fetch
43 _{Byte-wide Data Setup to CE1 , CE2 or}
t_OVCE1H
CE1N High During Opcode Fetch
44 _{Byte-wide Data Hold After CE1 , CE2 or}
t_CE1HOV
CE1N High During Opcode Fetch
45 _{Byte-wide Address Hold After CE 1-4,}
t_CEHDA
PE 1-4, or CE1N High During MOVX
46 Delay from Byte-wide Address Valid
CE 1-4, PE 1-4, or CE1N Low During
t_CELDA
MOVX
47 _{Byte-wide Data Setup to CE 1-4,}
t_DACEH
PE 1-4, or CE1N High During MOVX
(read)
48 _{Byte-wide Data Hold After CE 1-4,}
t_CEHDV
PE 1-4, or CE1N High During MOVX
(read)
49 _{Byte-wide Address Valid to R/ W Active}
t_AVRWL
During MOVX (write)
50 _{Delay from R/ W Low to Valid Data Out}
t_RWLDV
During MOVX (write)
51 _{Valid Data Out Hold Time from CE 1-4,}
t_CEHDV
PE 1-4, or CE1N High
52 _{Valid Data Out Hold Time from R/ W}
t_RWHDV
High
53 _{Write Pulse Width (R/ W Low Time)}
t_RWLPW
DS5002FP
(T_A = 0°C to70°C; V_CC=5V ± 10%)
MIN
MAX UNITS
30
ns
4t_CLK-35
ns
2t_CLK-20
ns
1t_CLK+40
ns
0
ns
4t_CLK-30
ns
4t_CLK-35
ns
1t_CLK+40
ns
0
ns
3t_CLK-35
ns
20
ns
1t_CLK-15
ns
0
ns
6t_CLK-20
ns
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