DS5002FP_1 Datasheet, PDF (18/29 Pages) Dallas Semiconductor – Secure Microprocessor Chip

AC CHARACTERISTICS
PARAMETER
SDI Pulse Reject
(4.5V < V_CC < 5.5V)
(V_CC=0V, V_BAT=2.9V)
SDI Pulse Accept
(4.5V < V_CC < 5.5V)
(V_CC=0V, V_BAT=2.9V)
SYMBOL
t_SPR
MIN
DS5002FP
(T_A = 0°C to70°C; V_CC=0V to 5V)
TYP MAX UNITS NOTES
2
µs
10
4
t_SPA
10
50
µs
10
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS (T_A = 0°C to70°C; V_CC=5V ± 10%)
#
PARAMETER
SYMBOL MIN
MAX UNITS
1 Oscillator Frequency
1/ t_CLK
1.0
16
MHz
2 ALE Pulse Width
t_ALPW
2t_CLK-40
ns
3 Address Valid to ALE Low
t_AVALL
t_CLK-40
ns
4 Address Hold After ALE Low
t_AVAAV
t_CLK-35
ns
14 RD Pulse Width
t_RDPW
6t_CLK-100
ns
15 _{WR Pulse Width}
t_WRPW
6t_CLK-100
ns
16 _{RD Low to Valid Data In @ 12 MHz}
@ 16 MHz
t_RDLDV
5t_CLK-165
ns
5t_CLK-105
ns
17 Data Hold after RD High
t_RDHDV
0
ns
18 Data Float after RD High
t_RDHDZ
2t_CLK-70
ns
19 ALE Low to Valid Data In @ 12 MHz
@ 16 MHz
t_ALLVD
8t_CLK-150
ns
8t_CLK-90
20 Valid Addr. to Valid Data In @ 12 MHz
@ 16 MHz
21 _{ALE Low to RD or WR Low}
t_AVDV
9t_CLK-165
ns
9t_CLK-105
t_ALLRDL
3t_CLK-50 3t_CLK+50
ns
22 _{Address Valid to RD or WR Low}
t_AVRDL
4t_CLK-130
ns
23 _{Data Valid to WR Going Low}
t_DVWRL
t_CLK-60
ns
24 _{Data Valid to WR High @ 12 MHz}
t_DVWRH
7t_CLK-150
ns
@ 16 MHz
7t_CLK-90
25 _{Data Valid after WR High}
t_WRHDV
t_CLK-50
ns
26 RD Low to Address Float
t_RDLAZ
0
ns
27 _{RD or WR High to ALE High}
t_RDHALH
t_CLK-40
t_CLK+50
ns
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