DS1390 Datasheet, PDF (14/24 Pages) Maxim Integrated Products – Low-Voltage SPI/3-Wire RTCs with Trickle Charger

Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
Hundredths-of-Seconds
Generator
The hundredths-of-seconds generator circuit shown in
the functional diagram is a state machine that divides
the incoming frequency (4096Hz) by 41 for 24 cycles
and 40 for one cycle. This produces a 100Hz output
that is slightly off during the short term, and is exactly
correct every 250ms. The divide ratio is given by:
Ratio = [41 x 24 + 40 x 1] / 25 = 40.96
Thus, the long-term average frequency output is
exactly the desired 100Hz.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. See Table 2 for the
RTC registers. The time and calendar are set or initial-
ized by writing the appropriate register bytes. The con-
tents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The day-of-week
register increments at midnight. Values that correspond
to the day-of-week are user-defined but must be
sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries
result in undefined operation. The DS1390–DS1393 can
run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12- or 24-hour mode-select
bit. When high, the 12-hour mode is selected. In the 12-
hour mode, bit 5 is the AM/PM bit with logic high being
PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20 to 23 hours). Changing the 12/24-hour mode-
select bit requires that the hours data be re-entered,
including the alarm register (if used). The century bit
(bit 7 of the month register) is toggled when the years
register overflows from 99 to 00.
Alarms
All four devices contain one time-of-day/date alarm.
Writing to registers 88h through 8Ch sets the alarm.
The alarm can be programmed (by the alarm enable
and INTCN bits of the control register) to activate the
SQW/INT or INT output on an alarm-match condition.
The alarm can activate the SQW/INT or INT output while
the device is running from V_BACKUP if BBSQI is
enabled. Bit 7 of each of the time-of-day/date alarm
registers are mask bits (Table 3). When all the mask
bits for each alarm are logic 0, an alarm only occurs
when the values in the timekeeping registers 00h to 06h
match the values stored in the time-of-day/date alarm
registers. The alarms can also be programmed to
repeat every second, minute, hour, day, or date. Table
3 shows the possible settings. Configurations not listed
in the table result in illogical operation.
Table 3. Alarm Mask Bits
REGISTER
08H
DY/DT
FFh
X
F[0–9]h
X
[0–9][0–9] X
ALARM REGISTER MASK BITS (BIT 7)
AM4
AM3
AM2
AM1
1
1
1
1
1
1
1
1
1
1
1
1
[0–9][0–9] X
1
1
1
0
[0–9][0–9] X
1
1
0
0
[0–9][0–9] X
1
0
0
0
[0–9][0–9] 0
0
0
0
0
[0–9][0–9] 1
0
0
0
0
ALARM RATE
Alarm every 1/100th of a second
Alarm when hundredths of seconds match
Alarm when tenths, hundredths of seconds match
Alarm when seconds, tenths, and hundredths of seconds
match
Alarm when minutes, seconds, tenths, and hundredths of
seconds match
Alarm when hours, minutes, seconds, tenths, and hundredths
of seconds match
Alarm when date, hours, minutes, seconds, tenths, and
hundredths of seconds match
Alarm when day, hours, minutes, seconds, tenths, and
hundredths of seconds match
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