CY8C26443 Datasheet, PDF (98/150 Pages) Cypress Semiconductor – Configurable Mixed-Signal Array with On-board Controller

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
10.9.2.3 Analog Switch Cap Type B Block xx Control 2 Register
AnalogBus gates the output to the analog column bus.
The output on the analog column bus is affected by the
state of the ClockPhase bit in Control 0 Register
(ASB11CR0, ASB13CR0, ASB20CR0, ASB22CR0). If
AnalogBus is set to 0, the output to the analog column
bus is tri-stated. If AnalogBus is set to 1, the ClockPhase
bit selects the signal that is output to the analog-column
bus. If the ClockPhase bit is 0, the block output is gated
by sampling clock on last part of PHI2. If the ClockPhase
bit is 1, the block ClockPhase continuously drives the
analog column bus.
CompBus controls the output to the column comparator
bus. Note that if the comparator bus is not driven by any-
thing in the column, it is pulled low. The comparator out-
put is evaluated on the rising edge of internal PHI1 and
is latched so it is available during internal PHI2.
AutoZero controls the shorting of the output to the invert-
ing input of the op-amp. When shorted, the op-amp is
basically a follower. The output is the op-amp offset. By
using the feedback capacitor of the integrator, the block
can memorize the offset and create an offset cancella-
tion scheme. AutoZero also controls a pair of switches
between the A and B branches and the summing node of
the op-amp. If AutoZero is enabled, then the pair of
switches is active. AutoZero also affects the function of
the FSW1 bit in Control 3 Register.
The CCap bits set the value of the capacitor in the C
path.
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Document #: 38-12010 CY Rev. *B CMS Rev. 3.22
August 18, 2003