CY8C26443 Datasheet, PDF (117/150 Pages) Cypress Semiconductor – Configurable Mixed-Signal Array with On-board Controller

interrupt will wake the part from sleep. The Stop bit in the
Status and Control Register (CPU_SCR) must be
cleared for a part to resume out of sleep.
Any digital PSoC block that is clocked by a System Clock
other than the 32K system-clocking signal or external
pins will be stopped, as these clocks do not run in sleep
mode.
The Internal Main Oscillator restarts immediately on exit-
ing either the Full Sleep or CPU Sleep modes. Analog
functions must be re-enabled by firmware. If the External
Crystal Oscillator is used and the internal PLL is
enabled, the PLL will take many cycles to change from
its initial 2.5% accuracy to track that of the External Crys-
tal Oscillator. If the PLL is enabled, there will be a 30µs
(one full 32K cycle) delay hold-off time for the CPU to let
the VCO and PLL stabilize. If the PLL is not enabled, the
hold-off time is one half of the 32K cycle. For further
details on PLL, see 7.0.
The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintain-
ing very low average power consumption. The sleep
interrupt may also be used to provide periodic interrupts
during non-sleep modes.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
Special Features of the CPU
CPU Running
Run
Analog
Sleep
CPU Sleep
Full Sleep
CPU not Running
Figure 32: Three Sleep States
August 18, 2003
Document #: 38-12010 CY Rev. *B CMS Rev. 3.22
117