CY8C26443 Datasheet, PDF (29/150 Pages) Cypress Semiconductor – Configurable Mixed-Signal Array with On-board Controller

I/O Ports
5.0 I/O Ports
5.1 Introduction
Up to five 8-bit-wide I/O ports (P0-P4) and one 4-bit wide
I/O port (P5) are implemented. The number of general
purpose I/Os implemented and connected to pins
depends on the individual part chosen. All port bits are
independently programmable and have the following
capabilities:
ƒ General-purpose digital input readable by the CPU.
ƒ General-purpose digital output writable by the CPU.
ƒ Independent control of data direction for each port
bit.
ƒ Independent access for each port bit to Global Input
and Global Output busses.
ƒ Interrupt programmable to assert on rising edge,
falling edge, or change from last pin state read.
ƒ Output drive strength programmable in logic 0 and 1
states as strong, resistive (pull-up or pull-down), or
high impedance.
ƒ A slew rate controlled output mode is available.
ƒ In high impedence, the digital input can be disabled
to lower power consumption.
Port 1, Pin 0 is used in conjunction with device Test
Mode and does not behave the same as other I/O ports
immediately after reset. A device reset with Power On
Reset (POR) will drive P1[0] high for 8 ms immediately
after POR is released because there is a CPU hold-off
time of approximately 64 ms before code execution
begins. It will then drive P1[0] low for 8 ms. This can
impact external circuits connected to Port 1, Pin 0.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
Port 0 and Port 2 have additional analog input and/or
analog output capability. The specific routing and multi-
plexing of analog signals is shown in the following dia-
gram:
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
August 18, 2003
Document #: 38-12010 CY Rev. *B CMS Rev. 3.22
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